1. Field of the Invention
The invention relates to field emission flat panel displays, and more particularly to methods for making field emission microtips with high uniformity for a high resolution matrix addressed flat panel display, and the resulting field emission microtips.
2. Description of the Related Art
In the area of computer displays, there is an increasing trend toward flat, thin, lightweight displays to replace the traditional cathode ray tube (CRT) device. One of several technologies that provide this capability is field emission displays (FED). An array of very small, conical emitters is manufactured, typically on a semiconductor substrate, and can be addressed via a matrix of columns and lines. These emitters are connected to a cathode, and surrounded by a gate. When the proper voltages are applied to the cathode and gate, electrons are emitted and attracted to the anode, on which there is catholuminescent material that emits light when excited by the emitted electrons, thus providing the display element. The anode is typically mounted in close proximity to the cathode/gate/emitter structure and the area in between is typically a vacuum.
U.S. Pat. Nos. 4,857,161 and 4,940,916, both to Borel et al, show basic methods for making field emission displays. In the latter patent, a resistive layer is added which covers the cathode layer and is under the microtips. The purpose is to prevent cathode destruction and improve thermal dissipation. This prior art structure is shown in FIG. 1, in which is shown cathode 10, dielectric layer 12, gate 14, the added resistive layer 16, and emitter 18.
The radius of the tip of emitter 18, and the size of gate opening 20, as shown in FIG. 1, are two of the critical parameters that can vary from one microtip to another. This variation leads to different characteristic operating curves among emitter tips. FIG. 2 illustrates the operating curves for two tips, Tip 1 and Tip 2. With no resistive layer 16, for a given operating voltage V.sub.c ', there will be a large difference in emission current between tips, since Tips 1 and 2 will operate at current levels I.sub.c1 ' and I.sub.c2 ', respectively. This difference causes non-uniformity of field emission device operation.
The added resistive layer 16 acts as a resistive load, as shown in FIG. 2 by the line 1/R. At operating voltage V.sub.c, there will be a much smaller difference in emission current between tips, which in FIG. 2 is indicated by emission current I.sub.c1 and I.sub.c2 for Tip 1 and Tip 2, respectively. The resistive layer of the related art also drops all voltage applied between gate and cathode in the event of a short circuit between gate 14 and emitter 18, and would isolate the short circuit point.
However, the addition of the resistive layer results in a higher operating voltage, in order to supply the voltage drop, typically 10 volts, across the resistive layer. The added resistive layer has a further disadvantage in that there is added power dissipation from the resistor. From the estimation of U.S. Pat. No. 4,940,916, the power dissipation from the resistive layer is between 1 and 10 microwatts per emitter. If a large area FED is operated in which there are millions of emitters, the power dissipation will be unacceptably high.
Some prior art patents show a dielectric layer that is added on top of the gate layer. These are for different purposes and are formed differently than will be described for the invention below. U.S. Pat. No. 5,151,061, Sandhu shows a second dielectric, but apparently this is only used as a process layer, and is not used in the final structure. In both U.S. Pat. Nos. 5,173,634 and 5,189,341, the dielectric layer is used to separate the two electrodes of dual-gate structures. Doan et al in U.S. Pat. No. 5,186,670 describe a focus ring 19 that is separated from the gate 15 by a dielectric. However, this focus ring would likely not be used over a large area in which many FE devices would be used. In U.S. Pat. No. 5,188,977, the dielectric layer 4 is used to separate the gate 3 from an attached substrate 9.